It looks like Microchip is adding a portfolio of RISC-V chips to its lineup.
Microchip has a large number of easy-to-use chips, including the 8-bit PIC and AVR families, the 32-bit SAM which includes Cortex-M0, M23, M4, M7 Cortex-A5 and (lol) the ARM9 family (still available today for all the Jazelle fans), and even a bit of a MIPS processor sitting around.
It looks like PIC64-GX will be Microchip's RISC-V.
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One of the cooler things in this announcement is the confirmation of linux4microchip.com support. linux4sam always was a good resource (and still is today: even for modern chips like SAM9x60).
Awesome to see. It'll be interesting to see what the level of support is. Does microchip float their own forked toolchain, or do Linux and Zephyr gain decent upstream support for these systems? As commented already, linux4sam started an extremely strong forward footing for the old Ateml arm chips; if microchip can tap that same kind of smart can-do engineers to get support for pic64 good that would really be a massive turbocharger for this effoet.
It's very very interesting & ultra-notable Microchip is shopping space-capable rad-hard editions, for mil use.
NASA JPL had selected Microchip and SiFive for making RISC-V SoC for future space missions so they probably planned to make similar chips for commercial customers. The one for JPL would be a RAD hardened versions.
Why would you need a forked toolchain when you're using absolutely standards-compliant SiFive RISC-V cores?
The same goes for Linux, Zephyr, FreeRTOS, NuttX and others ... all already work fine on RISC-V and have for years.
Also, Microchip's MicroSemi division (acquisition in 2018) has long been supplying rad-tolerant and rad-hard FPGAs to the space industry, and MicroSemi has been supporting SiFive cores as a soft core in their FPGAs since 2017 and as a hard core (penta-core 64 bit @ 600-666 MHz) in the PolarFire SoC since 2021.
Architecture support seems not risky, sure. Ideally it shouldn't be risky for any RISC-V CPU!
What's less clear is everything else. Will this have RISC-V OS-A Platform Specification specification so it is ACPI compatible, or will this require custom baked devicetree for all its uncore? Will that uncore all be sifive provided uncore stuff or is microchip perhaps going to reuse some of their existing peripherals from other efforts? Which peripherals & busses will and won't have support in Linux, Zephyr, and the variety of other rtos? Will that support be upstreamed alike how excellently & persistently linux4sam was?
As someone working for sifive I understand you want to present a good image, and I really hope the better cases do emerge here. I'm not worried about your RISC-V core working; it'll be great. I'm worried about how usable the rest of the chip will be & what level of support & upstreaming we'll see for that. Linux4sam is one of very very few arm players that has focused, for almost a decade now, on doing the right thing; most of the embedded ecosystem is fragmentary & not upstreamed & hard to use. Hence my comments & hopes.
MicroSemi is definitely well known for some rad capable devices, good call there. But that was for a very different line-up, different offerings. Having a PIC that's targeting such elevated use cases is, to me, quite notable.
"These space-grade, 64-bit multicore RISC-V MPUs are designed to deliver over 100 times the computing performance of previous models while maintaining high levels of radiation and fault tolerance."
This appears to be a 325-pin 0.6mm pitch BGA... or somewhere around that.
This is a full bore Linux-capable microprocessor supporting LPDDR4 and 1Gbit Ethernet. No where close to PC level, but maybe close to Rasp. Pi 1 levels.
Is this a reference to the processor in the Aronofsky movie Pi? Always found that scene really funny. They're hyping up this chip as the most powerful chip in the world (called "Ming Mecca") and then the guy opens up the box to show a chip with like 4 pins.
No. I've never seen the movie. We already have 32-bit microcontrollers in 8 pin packages [0]. Seems like 64-bit will also be coming down the pike eventually. If for no other reason than ease of toolchain development.
Mmmm ... CM0, 64 MHz, 8k RAM, 32k flash. I hit "Order direct" and it says "$0.93 | 10ku" which I take to mean you need to spend $9300 to get that price? I added one to my cart and it's $2.04.
If you can get by with 48 MHz, 2k RAM, 16k flash then there's the very popular RISC-V CH32V003 for which you need to spend $6.21 to get a $0.12 each price (50 units) [1]. Or for around $0.30 each (qty 20) you can get the CH32V203 with 144 MHz, 20k RAM, 64k flash, and USB. However the smallest package for that seems to be 20 pins.
But the '003 is getting very popular for cute little projects. It runs on both 3.3V and 5V, needs no external oscillator or crystal (but can use one), has Single Wire Debug, and is (along with the Puya PY32) the cheapest flash-based microcontroller you can get, allowing you to iterate your code without throwing away a chip every time.
A cute little €1 retro computer with PS/2 kb and bit-banged VGA:
If you really want luxury and can afford the 28-pins, the Microchip PIC32MK0128MCA028 has a 32-bit MIPS core running at 120 MHz, with a hardware floating point unit.
Why would this be easier to work with? 64 bit comes with additional costs that are mostly worthless for most applications, and toolchains around 32 bit are still plentiful. Most embedded interfaces are either 8 or 32 bit based today, too.
A lot of devices, such as RFID, are just Power (no ground, no data).
AC Power delivered by Radio provides both high-and-low voltage, which is captured by the end device. The end device can then respond over that same frequency by pulsing.
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There's also a variety of Power+Ground / 2-wire devices on the market if you are in DC (Data shared on the Power-line), which is kind of the idea behind 4-20 (draw between 4mA to 20mA depending on remote sensor information).
There's a wide variety of techniques to multiplex data "into" the power-line. If you absolutely must have a minimum number of pins, the absolute minimum is Power+Data and Ground (where Data is say... current based like 4-20mA protocol).
Power stays at 24V relative to ground, while the device changes its own current based on sensors to communicate. The power-line can measure the current.
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I know I was looking at a pulsed power / changing current protocol recently. Basically the current "pulses" based on the information it wants to send back. So its different than 4-20mA but still a similar concept (pulse-current-modulation for communication over Power+Data line vs Ground line.)
Microchip has a large number of easy-to-use chips, including the 8-bit PIC and AVR families, the 32-bit SAM which includes Cortex-M0, M23, M4, M7 Cortex-A5 and (lol) the ARM9 family (still available today for all the Jazelle fans), and even a bit of a MIPS processor sitting around.
It looks like PIC64-GX will be Microchip's RISC-V.
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One of the cooler things in this announcement is the confirmation of linux4microchip.com support. linux4sam always was a good resource (and still is today: even for modern chips like SAM9x60).
The RISC-V chip in quesrtion is: https://www.microchip.com/en-us/product/pic64gx1000