The neoTRNG provides a tiny (less than 70 LUTs) true random number generator for any FPGA. No device-specifc macros, libraries or attributes are used at all.
The quality of the generated random numbers has been verified with the "dieharder" random number test suite.
This is a tiny (less than 200 LUTs) Physical Unclonable Function hardware module for FPGAs. It provides a unique 96-bit "fingerprint" that can be used for security-related applications like key-generation or authentication.
The fingerprint is defined by the FPGA's semiconductor characteristics. The same bitstream will lead to different fingerprints when programmed to different FPGAs of the same type.
The whole design is written in platform-independent VHDL. No device-specific macros, primitives or attributes are used at all so the design can be implemented on any FPGA (tested on Intel, Lattice and (in-progress) Xilinx).
(the "platform-agnostic" concept/technique was taken from the NEPORV32 TRNG -> https://github.com/stnolting/neorv32)
A few bits of the raw fingerprint from the module are quite noisy, so a software post-processing is required. I have implemented a simple "averaging" mechanism here. Error correction codes might be much better - but I am still fighting with the theory behind them ;)
I have tested the design on several FPGAs with promising results (see GitHub page). However, I still need to do more long-time testing to ensure stability of the fingerprint.
You cannot really maintain that. The controller has to adapt. That is what the two reset signals are for. The synchronous one can be trigger by application logic (for example some sort of timer) to re-calibrate the touch controller.
I thought so, too. I have read about the Lattice MACH-NX having a secure enclave based on a RISC-V CPU, but it seems like this is just a soft-core CPU as well.
It is hard to compare two RISC-V cores if they do not have similar configuration options. For example: what kind of ISA extensions, supported traps, custom extensions, CSRs, etc. does VexRiscv "SmallAndProductive" configuration include?
I like that it is written in VHDL and provides an all-in-one package: cpu, soc and software
It’s a basic R32I configuration, without traps or branch prediction enabled, but with 5 pipeline stages and all bypass paths included, so it executes straight code at 1 instruction per clock.
The VexRiscv also comes with a bunch of full featured SOCs.
The VexRiscv is configurable to the extreme and it’s extremely easy to do so. There are tons of other configurations in the same directory, from even smaller to full Linux SMP configs. It’d be trivial to create one that has the same configuration as this one and compare.
SpinalHDL supports both Verilog and VHDL output, so you’re covered there as well.
It’s not native VHDL, of course, so if you want to understand the code at the VHDL level instead of just wanting to use a soft core CPU, it’s probably not for you.
Those who just need a CPU for a non-Scala environment (e.g. Litex) just pre-generate a whole bunch of configurations and then pick what they need for a certain use case.
Since there's no clear connection, I've taken Show HN out of the title now. But if it actually is your personal work, let us know and we'll be happy to put it back.
If it's not your work, it's still a fine submission, it just needs to not say "Show HN" in that case.
A size-optimized and highly customizable soft-core micorcontroller based on a rv32[i/e][m][a][c][b][Zfinx][Zicsr][Zifencei] +[u][PMP][HPM] CPU.
The SoC includes internal memories/caches together with common peripherals like timers, serial interfaces, Wishbone/AXI-connectivity, GPIO/PWM, a TRNG and even a dedicated Neopixel LED interface.
Written in platform-independent VHDL
Tested on Lattice, Intel and Xilinx FPGAs
Full-blown data sheet
Doxagen-based documentation of the software-framework (including FreeRTOS port)
The quality of the generated random numbers has been verified with the "dieharder" random number test suite.