I tried it out and it has some issues with my native speech. I grew up with more Taiwan mandarin but I know the Beijing standard and the recognizer was flagging some of my utterances incorrectly.
Funny enough when Intel and DEC settled their lawsuit Intel got StrongARM[1] from DEC which was pretty fast for its time. It was a pretty cool, literally, chip that didn't need a heatsink. I had a Shark set-top appliance prototype. The offical name was DNARD — Digital Network Appliance Reference Design.
The hardware folks at HP were big into the outdoors. The story went that it was named Halfdome but customers outside the US who weren't familiar with Yosemite would ask where the other half was.
Did the PA-RISC shops run their old PA-RISC code with the Aries emulator?
One of the selling points for HP users was running old code via dynamic translation and x86 would just work on the hardware directly.
Another fun fact I remember from working at HP was that later PA-RISC chips were fabbed at Intel because the HP-Intel agreement had Intel fabbing a certain amount of chips and since Merced was running behind... Intel-fabbed PA-RISC chips!
I lost track of it but HP, as co-architects, had its own compiler team working on it. I think SGI also had efforts to target ia64 as well.
But the EPIC (Explicitly Parallel Instruction Computing) didn't really catch on.
VLIW would need recompilation on each new chip but EPIC promised it would still run.
In the compiler world, these HP compiler folks are leading compiler teams/orgs at ~all the tech companies now, while almost none of the Intel compiler people seem to be around.
Are you sure about that? If my memory serves, a lot of the Intel compiler people were transferred from HP? At least in the Fortran world, the Fortran frontend for the Intel compiler traces it's lineage back to DEC Fortran (for VAX and later Alpha) -> Compaq Visual Fortran (for Windows) -> Intel Fortran.
Itanium was compatible with x86. In fact, it booted into x86 mode. Merced, the first implementation had a part of the chip called the IVE, Intel Value Engine, that implemented x86 very slowly.
You would boot in x86 mode and run some code to switch to ia64 mode.
HP saw the end of the road for their solo efforts on PA-RISC and Intel eyed the higher end market against SPARC, MIPS, POWER, and Alpha (hehe. all those caps) so they banded together to tackle the higher end.
But as AMD proved, you could win by scaling up instead of dropping an all-new architecture.
* worked at HP during the HP-Intel Highly Confidential project.
Having briefly worked at HP on the IA64 effort IIRC the PA-RISC chips fabbed at Intel were the side-effect of the Itanium agreement. HP was owed a certain volume of chips and since Merced was very delayed they had to make those chips for HP.
Not to detract form your point, but Itanium's design was to address the code compatibility between generations. You could have code optimized for a wider chip run on a narrower chip because of the stop bits.
The compiler still needs to know how to schedule to optimize for a specific microarchitecture but the code would still run albeit not as efficiently.
As an aside, I never looked into the perf numbers but having adjustable register windows while cool probably made for terrible context switching and/or spilling performance.
I find it somewhat ironic that many years ago HP’s PA-RISC chips were fabbed at Intel because contractually they had to supply chips due Itanium not yet taping out.
But maybe it was more of an early foreshadowing. I had a housemate that worked on their internal CAD tools and it also sounded like a bit of a mess with NIH syndrome. (20+ years ago)
It’s in the Jargon file. Your comment made me remember this bit:
Hackers at HP/Apollo (the former Apollo Computers which was swallowed by HP in 1989) have been heard to complain that Mr. Packard should have pushed to have his name first, if for no other reason than the greater eloquence of the resulting acronym.
