Yes. There's been good work in that space to make some of them use hardly any power where unnecessary and asynchronous ones (eg Achronix) could take it even further. Yet, always will be behind on ASIC's on power usage. I don't see them getting around that.
You're thinking of Structured ASIC's: FPGA-like devices that are configured by via's or metal layers. They knock some layers and material issues off the design, lowering costs. They use less power, are faster, and have lower unit costs than FPGA's. So, it seems win win. They primarily didn't take off because lower-cost tooling and multi-project wafers made low-end ASIC's cheaper than before. Still a good option to consider if ramping up volume on a FPGA-proven design. I've always said best thing to do for open-hardware is a matching 45-90nm FPGA and S-ASIC architecture with plenty of pre-proven blocks (esp I/O and memory).
Anyway, here's you a list of some for your own research. eASIC is longest running plus has ability to prototype chips for you without mask costs. That's awesome. Triad is extending concept to analog/mixed-signal at about $400k a projects last I heard. Others I know nothing about.
Xilinx advertises "EasyPath" as an ASIC alternative, but I'm pretty sure that's just a form of cost reduction for the exact same FPGA chips (by enabling them to use defective chips where the specified bitstream doesn't hit the defect?) rather than an actual "hard" option.
Now that is interesting. Ive neither heard of nor though of that in FPGA's. It's a proven trick given it was used by AMD for Tri-Core processors which were Quad-Core processors with a faulty, disabled core. Now I'm wondering if I should ask more vendors about for discounts haha.
