How do you manage cached and uncached memory accesses? There has been some discu... | Hacker News

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		vanjoe on July 20, 2017 \| parent \| context \| favorite \| on: An FPGA-friendly 32-bit RISC-V CPU implementation How do you manage cached and uncached memory accesses? There has been some discussion lately on the mailing lists about this

Dolu on July 20, 2017 [–]

Cached an uncached memory access are currently staticaly specified by range :

https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s...

From 0xF000000 to 0xFFFFFFFF access will be uncached.

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