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I agree with the gist of your comment but pedantically want to take issue with this ;) :

> That is, the basic premise of hardware process isolation is that a process cannot have any knowledge of what another process is doing, or whether it even exists,

Side channels such as the cache and timing break that promise.

This has been known forever. Nobody can contemplate a decent CPU without cache!

The thing that spectre and meltdown have demonstrated - obvious in hindsight! - is that CPUs that speculate can use this side channel to exfiltrate secrets in shockingly powerful ways that are really hard to defend against.

We can do things to stop speculated loads leaking via cache hoist/mru/evict/etc and make chips immune to these powerful attacks.

Eliminating the general cache side channel is a damn sight harder and still an open problem.

The cache attacks against crypto systems eg scrypt are fascinating just like spectre.



To summarize, if I may, your observation using the familiar template:

Low-latency memory access, low-latency conditionals, secure isolation ... choose two.


>> Nobody can contemplate a decent CPU without cache!

I like to contemplate a huge SRAM on die. Get rid of caches and speculation entirely. Of course that doesn't work for really big systems, but we might one day have a full 32bit address space available like this. Now hopefully you can contemplate it too!




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