I don't know much. Just getting into FPGAs my self. But from my understanding you could swap out the crystal for a faster one. Most of the FPGA boards I am looking at only come with a 50mhz clock.
There is some complications around changing the clock. It seems to have to do with the complexity of the hdl you load into the FPGA. Many of the boards shipping with 50mhz crystal can easily do over 100mhz.
You wouldn’t swap out the crystal, you’d use the internal PLLs to generate whatever clock you want. Much easier!
And you are essentially correct, there is a maximum clock speed for any design, and it has to do with how complex your design is. Essentially, what’s the longest path in your design? Your clock must be slow enough to allow a change to propagate through that path. Pipelining shortens this path by creating registers along it, which are clocked by your clock. When a register is clocked, it stores the value in its input side, and outputs that value on the output side.
Generally speaking, what determines the "clock speed" for FPGAs is a combination of the design of the FPGA device plus the complexity of the design being implemented on it.
Let's imagine you design a CPU on an FPGA. One way to measure the speed of that design is to look at the speed of the slowest operation of that CPU. The clock needs to be set at the speed at which the slowest (most complex) operation can reliably run at.
Most modern FPGAs have a PLL (or DLL) implementation [0] which can multiply the external clock by some rational number. e.g. 50MHz external crystal clock is multiplied by 5/2 to obtain a 125MHz internal clock.
There is some complications around changing the clock. It seems to have to do with the complexity of the hdl you load into the FPGA. Many of the boards shipping with 50mhz crystal can easily do over 100mhz.