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From the Readme:

"While developing Ariane it has become evident that, in order to support Linux, the atomic extension is going to be mandatory. While the core is currently booting Linux by emulating Atomics in BBL (in a single core environment this is trivially met by disabling interrupts) this is not the behavior which is intended. For that reason we are going to fully support all atomic extensions in the very near future."

Is the atomic extension mentioned here something like the LOCK prefix in x86, i.e it just lock the bus for the instructions that follow? I'm guessing this is non-trivial to implement?



Load-reserve, store-conditional, and atomic memory operations (e.g., AMO-ADD).


Thanks, I had to look up the AMOADD instruction. For anyone else who's interested, this is nice RISC-V reference card:

https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/...




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