And now compilers will make sure your data structures are aligned. Adding circuitry and compromising performance for lazy programmers is a bad idea. This is one thing RISC-V has carried over and I'm not sure they have justified the decision to do so.
In some cases, packing data structures with no alignment is more important because it means more data fits in the cache, and cache misses are extremely slow in comparison.
Modern x86 is mostly insensitive to data alignment, since it fetches internally in cacheline-sized blocks (I believe it's 64 bytes) and a very wide barrel shifter is used to access the desired bytes. There's a tiny (single-digit cycles) extra time when the element straddles two cachelines (assuming both lines are in cache)
The justification in the RISC-V spec is that it might make porting some software easier. They also say that unaligned loads/stores may be non-atomic and take much longer than aligned accesses -- allowing firmware emulation on simple implementations. The current atomic extension doesn't allow unaligned at all -- though I think there's an extension to allow atomic unaligned accesses in the works.
One could argue that adding circuitry and compromising performance for lazy programmers is the central idea of cpu design nowadays. The ones that assumed smart compilers or assembly programmers fell by the wayside in the market. VLIW cpus, Cell, Itanium etc.
