Hacker Newsnew | past | comments | ask | show | jobs | submitlogin

AVX(2) definitely had the power-up stall on many chips, including all client Skylake I think.


No, it had reduced throughput of AVX instructions while the ALUs powered up. Not a stall.


Yeah maybe you are right for Skylake client, I haven't tested carefully there, but I'll probably get around to it. This thread [1] indicates that it may have only been Haswell that had the halted portion.

On to Skylake-SP, however, that chip is reported to have both reduced throughput and fully halted periods in [2].

Some have speculated it has to do whether chips have an integrated IVR: the models with integrated IVR having less capability of handling high dI/dt events. I don't know about that though (Skylake-SP still has external VR, right?).

[1] https://www.agner.org/optimize/blog/read.php?i=378#378 [2] https://software.intel.com/en-us/comment/1926876#comment-192...




Guidelines | FAQ | Lists | API | Security | Legal | Apply to YC | Contact

Search: