The title of the course is misleading, as it suggests that NAND gates are the only required primitive, whereas the course later introduces DFF gates, without which you cannot escape the parallelism of chips.
Thanks, that page is nice, but it too emphasizes that you also need a clock. That's essential and it was the point I was trying to make. For example, a thing that is usually glossed over in OS courses (in favor of, let's say, scheduling algorithms and such) is that you simply can't make preemptive multitasking out of pure code - and later when you ask yourself how is it that such a phenomenon is possible in the first place you learn that chips are inherently parallel, that sequential code is an abstraction over that so that one can have some sort of law and order, and only then interrupts enter the scene so that one may break that order when needed, e.g. for preemption.
You can make a clock easily enough: two NAND gates, two resistors, two capacitors. If you use parasitic components you will get a pretty wild resonance so better to nail it down by using something a bit more stable. But in principle it will work just fine.
Agreed on the 'preemtive multitasking' bit, but that has little to do with this subject. And it is kind of embedded in the name, you need something to do the pre-empting which by definition has to come from outside.
But building a functional computer with just NAND gates is absolutely possible, even if there are better ways, just like you could use Brainfuck or combinators to do meaningful computation. The whole idea of the course is not to give some kind of purist model for computation but to show that the essence of a computer can be boiled down to some very simple building blocks. So the title of the course is misleading only if you want to pick nits. Course titles are made to attract students and to give broad cover to what the course is all about, not to satisfy language purists.
Couldn't you in theory build a clock purely from nand gates? You create a cycle of nand gates where the output of one is tied to both inputs of the next. If the cycle have an uneven number of nand gates, each nand will oscillate with a period depending on the length of the cycle.
You can make a DFF from NAND gates, though it's pretty obvious the simulator they wrote for the class can't perform that emulation. I was a little put off from the class when they tried to explain why they didn't want to cover them "because they were too complicated". It's pretty obvious to anyone who understands them that they're not significantly more complicated than the rest of the material. I gave up on the class right there, thinking the instructors and the rest of the class would be a lot of the same BS. I'm glad I got over it and completed the rest of the class as it was pretty fun.
And one thing that is said even less is why NAND? You can do it all with NOR gates as well if you want. The reason for NAND has to do with the switching speed, pMOS switches quicker in parallel (either transistor can get the current flowing) and nMOS switches quicker in series (either transistor can stop the current flowing); this is how a NAND gate is wired. NOR gates on the other hand have the worst of both.
The fact that nMOS switches off quicker is why the most common form of dynamic logic (as opposed to static logic) implements, in effect, the bottom half of the CMOS in nMOS and the upper half using a capacitor; which holds the charge and hence pull up for the length of the clock cycle (which is why dynamic logic CPUs can't be single stepped in hardware, the clock speed is too low to hold a charge).
During my intro to computer engineering course, lectures touched on why NAND gates, and the conclusion was that you can build anything you need in a basic computer using NAND gates. It boils down to expense. A BOM (bill of materials) with fewer line items tends to be cheaper.
This doesn't really hold in today's world of silicon prints, but at the start I think it was price that drove the decision.
Actually if you take an XOR gate with a naive translation into NAND gates you would use 20 transistors, but if you don't need a large fan out from the output you can actually do it with 6 transistors using a pass gate layout (which is neither NAND nor NOR). So typically you don't use NAND vs NOR because of transistor count.
Don’t NAND take up less room too? It took a CMOS course several years ago, and laid out a 16x16 shift register. The NAND was simple, orthogonal strips of gate metal and channel. The NOR required a parallel structure with more area.
