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Any idea what ARM cores these are based on? A5x? A7x?

A76 would be pretty interesting...




Looks like A72. Here's the cpuinfo:

  processor	: 0
  BogoMIPS	: 166.66
  Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
  CPU implementer	: 0x41
  CPU architecture: 8
  CPU variant	: 0x0
  CPU part	: 0xd08
  CPU revision	: 3


Too bad, A72 is the sort of thing found in $49 SBC's these days. For the price, it would have been nice to see at least A73, but at least its not an A53.


A73 isn't for servers and I don't see any server/embedded SoCs with A75 yet, so Amazon isn't exactly behind.


True, most server ARM processors that come to mind are custom (or at least semi-custom): Ampere, Centriq, ThunderX2. Trying to map them to A72/73/75/76 is perhaps short sighted since those are primarily smartphone cores - we'll have to wait and see how they perform in real world tests.


> at least its not an A53

Indeed. A72 is like the minimum viable core :) It's no eMAG or ThunderX2, but it's kinda comparable to the original ThunderX.


Jeff has to make take his cut from somewhere after all


Probably should have done a lscpu instead. On recent arm distro's lscpu knows how to decode the part/variant/etc and it also pays attention to the cache and numa topology.


What does cpuinfo display when the CPU lacks the cpuid feature?


Arm processors don't have a cpuid instruction, but they do have a number of ID registers that provide similar information (e.g. MIDR_EL1, REVIDR_EL1).


lscpu output:

Architecture: aarch64

Byte Order: Little Endian

CPU(s): 8

On-line CPU(s) list: 0-7

Thread(s) per core: 1

Core(s) per socket: 4 Socket(s): 2

NUMA node(s): 1

Vendor ID: ARM

Model: 3

Model name: Cortex-A72

Stepping: r0p3

BogoMIPS: 166.66

L1d cache: 32K

L1i cache: 48K

L2 cache: 2048K

NUMA node0 CPU(s): 0-7

Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid


Here's lstopo output for the largest one, for good measure: https://instaguide.io/info.html?type=a1.4xlarge#tab=lstopo though there's nothing terribly surprising.


That seems unlikely, ARM topology has been a bit messed up. So lstopo is confusing what are probably cpu clusters with sockets.




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