PI code on x86 is provided by Intel. You can't ever open source it.
Coreboot, like other offerings, sets up the basic stack and jumps to Intel provided blob, which then jumps to the provided hook in Coreboot when a particular part of initialization is done. DDR controller, microcode patching are all done at start-up via this mechanism.
Intel claim one reason that you just have to trust their binary blob PI/FSP to do these kinds of things is because at each stepping release of a given CPU there are different early boot errata and microcode abilities until microcode is loaded from flash. It's a bit of a stretch, but the insulation can be thought of as useful in the right light.
Coreboot, like other offerings, sets up the basic stack and jumps to Intel provided blob, which then jumps to the provided hook in Coreboot when a particular part of initialization is done. DDR controller, microcode patching are all done at start-up via this mechanism.