It won't stop here. Apple will put ARM in their laptops, and they will help usher in a new era of more power efficient computing in a way that x86 simply cannot, in whatever shape. Just wait and see.
I don't think that ARM is as clear a win in high performance areas as you seem to think. ARM does let you get away with not having most of the decode logic that an x86 has to carry around, but thats pretty small penuts compared to out-or-order logic with a decent reorder window size, or a wide execution cluster with the associated bypass network.
And while instruction predication does let you avoid a lot of branching nearly for free in the ARM architecture it makes out of order logic much less effective because now there are a lot more dependencies between instructions. That was the reason the Alpha team decided not to use predication, even though they were familiar with the idea. Its also why the Itanium, an in order architecture, used predication.
Yep, taking a look at a modern x86 core in 32nm (and 22nm is just around the corner), the x86 decoding is now just a tiny part of the core. Intel has been been picking low-hanging fruit and not trying particularly hard to make things very low power. The current area of work is GPU integration with CPU on the same die (see Sandy Bridge).
Consumer electronics is driven by volume & price, so all we are really seeing is small, low power cores becoming acceptably fast for mainstream computing.
No, he detailed specific differences in the branch predictors of the two mentioned architectures. Branch prediction is part of the microarchitecture of a CPU, not its ISA. These two should not be confused.
As the other commenter pointed out, I'm talking about instruction predication (also called conditional execution) instead of branch prediction. In any ISA you have branches that might or might not execute depending on some conditions. With ARM, the first four bits of every single instruction - not just branches but loads and stores, addition and subtraction, etc - are used to specify under what conditions the instruction will be executed - so you can have small 'if' statements that don't actually need any branches when they're compiled.
All that is really pretty awesome if you're designing your processor to go in order, but if you want to try out of order execution it becomes more complicated. Now you have to check every instruction to see if its predicated, and if it is you now have a new dependency on the previous arithmetic instruction even if there isn't any data dependency between the two. Of course you could argue that if you find a predicated instruction in ARM code then its replacing a branch that would be in x86 code, and that overall your job is no harder. And you could go back and forth arguing over it.
The important thing to remember, though, is the things that give the ARM ISA inherent advantages when you're making low power, in order processors aren't necessarily advantages when you're talking about high performance, high power processors.
If the inefficiency of the x86 ISA was a killer, we'd all be using Alpha, PowerPC, SPARC, PA-RISC, or Itanium processors today. The basic argument you're giving is about 20 years old by now and the market has seen it tested.
ARM claims their new Cortex-A15 will provide five times the performance of existing smart phones. So the resources and interest are definitely out there.
Probably just as important for a MacBook replacement: "The introduction of Large Physical Address Extensions (LPAE) enables the processor to access up to 1TB of memory."
A typical improvements for microarchitecture is a factor of 2, spread between different units. For example, we could speed up full word adder (most common roadblock for higher clock frequency in current CPU's) by 10 percents, add scoreboard that allow us to issue 1.3 instructions in average load, add bypass logic that allows us to cut delay by 1/5 (5 cycles for pipeline) and we get 1.11.31.2=1.72 of our previous speed.
I assume that ARM already have all those fancy bypasses and scoreboards. So how would they get that 5 times speed up?
I think it will be true for some special cases, like Javascript interpreter or video decoding. I bet on JS.
It is hard to speed up a mature architecture by five times.
Trying to parse their marketing material the best I can, the 5x refers to dual-core configuration clocked at 1.5GHz. More than 8 cores are also available and with clocking from 1 to 2.5 GHz.
Are CPUs even that much of a laptop's power budget these days? I know that the transition from CCFL to LED backlighting helped, but I think displays are still the biggest power draw. If you look at an Atom system, the chip with the biggest heatsink isn't the CPU, it's the chipset (or the GPU if it's discrete).
It seems to me that in order for an ARM processor to be viable for something like the MacBook Air (which is already using all the easy power-reduction measures like LED backlights and SSDs), the ARM chip will have to be twice as fast and draw half as much power as an Atom.
Being able to run Windows is a key competitive advantage for Macs now, and Windows (due to the problems of application support) will likely never run on ARM. Hence, neither will Macs.
x86 has always been predicted to fall behind competing architectures, and it's always kept up--at least for personal computers--because of the large vested interest in keeping all that x86 code running. History is littered with better-architected CPUs that couldn't beat x86. ARM survived because ARM is an embedded processor, and PPC survives as an embedded processor, but Apple's been down the road of trying to shoehorn an embedded processor design into Macs before, and ended up migrating to x86.
How will this affect BootCamp? Won't it put a stop to the ability to run Windows natively?
One of the factors that help people move across to OSX seems to be the knowledge that they can still install Windows if they need/desire. Perhaps Apple will buy Parallels and include it as part of the OS (although VMWare will have a case if they see this as being anti-competitive)?
