The author seems to not know the difference between the chip and the ISA - Instruction Set Architecture. How this is implemented in silicon (or other substrate) does not seem to have been released, so you'd have to create your own cores, cache, memory interface and all that jazz. It does mean that RISC-V chips could be used as a starting point, because they already implement all that, but with a different ISA. However, it's probably non-trivial to implement a different ISA on an existing chip design. AMD did it with their early Athlon chips, by using a translation layer, but that's not the most efficient way to do it...