STM32 has special its ART accelerator cache to prefetch instruction lines from flash and significantly reduce wait states. A clone can't replicate the same performance with a bog standard flash peripheral.
I know about ART. I actually have some contributions to the STM32F4 reference manual as my team had access to pre production silicon. There's bugs in the prefetching on that thing on early revs and you need to flip a chicken bit.
I still don't see anything in there that's not the usual way flash is accessed in cases where it's mapped into the address space for XIP applications. Hell, a lot of the time people will stick something nicer than a dog simple direct mapped cache like ST's implementation.
