I'm 25 and consider myself very well-versed in C (though I still have to consult the C99 spec from time to time). When I was learning to program modern computers around the turn of the century, it was the only "serious" language for writing desktop apps (I had recently "graduated" from VB4). I then refined my skills over the course of my electrical & computer engineering degree and a short stint in the EE industry, where it's very much alive as THE language for microcontrollers (and last I heard, a variant called SystemC was (sadly) replacing Verilog and VHDL for use in ASIC/FPGA design).
FPGA designer here. I don't think it's accurate to claim that SystemC is replacing VHDL and Verilog for ASIC/FPGA design. I view SystemC as a niche tool to allow software engineers to dabble in hardware design. I use C for embedded software, but would never dream of designing hardware in anything else except pure HDL. It's a bit like trying to write a letter in a foreign language using Google Translate-- the results are non-optimal and often comical.
While trying to learn HDL I felt like Verliog was more naturaly than VHDL. I didn't bother trying to learn SystemC or anything, organizing a project on Quartus or ISE is hard enough as it is with Verilog.
I need to go back to dabbling with my little Spartan3E board though.
SystemC was about (co)simulation - for building models of hardware. ALthough there were some tools for converting SystemC into HDLs, I don't think they ever really took off.
