Well those costs are mainly related to adding support for another memory standard, but i'm suggesting ECC become the standard with non-ECC being dropped. The BIOS/testing cost would be unaffected, they would just be testing only ECC memory.
Realistically the mainstream CPU manufacturers have ECC solutions, so including them in the mainstream processors shouldn't be a huge issue, it's just a market segmentation ploy to exclude the feature from the consumer processor designs.
> i'm suggesting ECC become the standard with non-ECC being dropped.
I think the cost pressure is too high. Early IBM PCs required parity ram (a 9th chip to store if the sum of bits was even or odd), and would fault if the value was incorrect on reads. Ram module manufactures made innovative fake parity modules that calculated the parity value on access, replacing the 9th ram chip with a very simple circuit and saving money.
It would be hard to convince the whole industry not to make fake ECC ram, if ECC was mandatory.
Fake ECC as you put it serves a purpose, it protects the bus interface. Which is one of the failure points on modern machines, and is why sometimes to fix ram/qpi/etc errors you end up replacing the motherboard.
We will have to see with DDR5 (because it supports "internal" ECC) if its worth it to the memory industry to build RAM that is internally denser, but more error prone (as is the case with modern flash) or continue to attempt to build 100% reliable ram (and failing).
I'm betting some clever person figures that out. Which leaves only the memory bus itself unprotected. Which IMHO, is foolish and serves only to create product segmentation. So, for a DDR5 dimm with internal ECC, generating bus ECC should be a trivial addition.
> that calculated the parity value on access, replacing the 9th ram chip with a very simple circuit and saving money.
> It would be hard to convince the whole industry not to make fake ECC ram, if ECC was mandatory.
Assuming you don't use memory-mapped IO, that's easy to fix. On startup, generate 4 random bits a,b,c,d. Parity bit is data line 4a+2b+c, with d?even:odd parity, data bit 4a+2b+c is on data line D8. ECC on 64/72 uses more random bits, but is otherwise similar, although for modern chipsets it would probably have to be scrambled in the northbridge or southbridge (or equivalent) rather than the CPU, to allow for DMA and such. Note that there's no gate delay involved here; the multiplexing can be done with pass transistors.
Realistically the mainstream CPU manufacturers have ECC solutions, so including them in the mainstream processors shouldn't be a huge issue, it's just a market segmentation ploy to exclude the feature from the consumer processor designs.