Older AMD CPUs, such as the K5 were RISC CPUs with an x86 decoding frontend:

https://en.wikipedia.org/wiki/AMD_K5

Isn't that arguably true for all modern x86 CPUs, including Intel's?

That is true, although it's worth saying that (if I'm not mistaken) outside of patents we don't really know what the micro-ops do i.e. RISC possibly isn't the best descriptor.

The microarchitectural classification of a modern CPU is slightly murky, i.e. a modern x86 has a pipeline a la the first one to do so, but the way the CPU actually uses it is completely different (i.e. OoO, speculative etc.)

Transmeta was VLIW scheduled at runtime, though, right?

It's a slightly different kettle of fish to do, although the decode itself is presumably the same.

Funny, I spent the last few nights reading about Transmeta's chips.