Seems to me that 'registers' are just really fast memory locations that get referenced by a 'stunted' address space in order to fit into most instructions. In other words, this is not a conceptual necessity. It exists because it's hard to build HW which can access all memory locations really fast. This hardware limitation leaks into software via hacks like 'registers'. Dealing with this hack is what forced Armv8 to remove PC as R15; "In the A32 and T32 instruction sets, the PC and SP are general purpose registers. This is not the case in A64 instruction set."
There is a lot of other HW crud that leaks into sw for dubious reasons. For example, although 'wasteful' if every memory location had tag bits -- hardware enforced -- capabilities would layer naturally. More sophisticated memory protection would be possible.
Instead, we have these von Neumann archs hellbent on winning some synthetic benchmark. Will the computer-using community ever demand some sacrifice in overall potential "adds-per-second" to enable better security and to support better abstractions? Sadly, I doubt it. Even Risc-V is a baby step.
Do note that most processors have a physical register file that is several times larger than what they expose in the ISA.
ARM has various mechanisms in flight for tagging; there's already PAC shipping on certain chips and MTE seems like it might be on the horizon. More advanced efforts like Morello are being evaluated, too.
> Seems to me that 'registers' are just really fast memory locations that get referenced by a 'stunted' address space in order to fit into most instructions. In other words, this is not a conceptual necessity. It exists because it's hard to build HW which can access all memory locations really fast.
Registers are unavoidable. Even if you could directly address the whole memory space on every instruction, even if it was all "really fast", the hardware would still need to read the input operands from memory into internal registers, and store the result into an internal register before writing to memory.
There is a lot of other HW crud that leaks into sw for dubious reasons. For example, although 'wasteful' if every memory location had tag bits -- hardware enforced -- capabilities would layer naturally. More sophisticated memory protection would be possible.
Instead, we have these von Neumann archs hellbent on winning some synthetic benchmark. Will the computer-using community ever demand some sacrifice in overall potential "adds-per-second" to enable better security and to support better abstractions? Sadly, I doubt it. Even Risc-V is a baby step.