At that distance, depending of the frequency of those buses, it could have some distortion and some latency due to being a transmission line. If this happened, the team that made that CPU would add some kind buffers at the receiving side to get the data at a correct time, and that could be most of the induced lag.
Adding that to the fact that the three cores have a shared common bus, and there are gone to be some kind of signalling about who is using it (that we don't know), this could be reasonable.
The Xbox 360 CPUs works at 3.2 GHz, that's 0.3125 ns per cycle, and four cycles make those 1.25 ns. I won't be surprised if those who made the CPU designed to have 4 cycles of delay to cores 1 and 2 to be sure there isn't any kind of glitch reading the data from the port.
You meant 0.3125ns per cycle, the rest of your comment triggered a thought:
It's common in FPGA/microcontroller designs to have 'input synchronizers' on inputs from long digital lines (on any input where you can't guarantee synchronicity) to prevent metastability problems, especially when crossing clock domains. I think that's likely the case here, there are both long lines and different clock domains.
Adding that to the fact that the three cores have a shared common bus, and there are gone to be some kind of signalling about who is using it (that we don't know), this could be reasonable.
The Xbox 360 CPUs works at 3.2 GHz, that's 0.3125 ns per cycle, and four cycles make those 1.25 ns. I won't be surprised if those who made the CPU designed to have 4 cycles of delay to cores 1 and 2 to be sure there isn't any kind of glitch reading the data from the port.