Yes, I'm fully aware that these things take time, and I even mentioned some of what you did in the article. As far as what's actually available, I appreciate the heads up on the ICE SoC. That's a new one to me and does sound like it would be a better fit for this application. But the rest of what you mentioned reads like the same sort of vague future promises that have swirled around RISC-V since the beginning.
I don't have anything personally against RISC-V, and given that OpenPOWER has all but ceded the low-end for the time being it might as well be RISC-V that fills it. What's around certainly seems a better fit for low-power and mobile.
But the point is what's around. Sure, you don't hear as much about ARM, x86 or other projects at earlier stages, but that's also because the hype around RISC-V has encouraged a lot of people to make a lot of promises early that don't go anywhere (I mentioned Micro Magic for a reason). That can't be good for the ecosystem. Cores are only as good as the ones that make it to tape-out, and real engineers ship.
If you read Micro Magic's press release it was clear (at least to me) that it was just a lab demonstration of their design tools and process technology and absolutely nothing like a product and not intended to be. If some of the press said something different that's not really Micro Magic's fault.
I'm not sure what you mean by "vague promises". As far as I can see (and I've been following them for years), the major players such as Andes, SiFive, Western Digital, Alibaba (T-Head) carry through with what they promise. Sometimes they don't meet the schedule they initially announce, but that happens with everything.
I sure wouldn't count Horse Creek as a "vague promise". Future chips from StarFive -- sure.
Companies normally announce a CPU core when it's ready for licensing by chip designers. That means the RTL design is complete and is running at 10's of KHz in software simulation (e.g. Verilator) and 10's of MHz in a FPGA (or faster in the ultra-expensive stuff the EDA houses sell). Linux is booting, Dhrystone and Coremark and SPEC have been run. The design works and the performance per MHz is known with basically 100% accuracy. The only remaining question is what MHz a customer will get on some silicon process and with how much effort at physical layout.
Well, and the question of whether they get any customers, and whether such customers make a product they announce, or something we never hear about because it is used internally in another product.
I don't have anything personally against RISC-V, and given that OpenPOWER has all but ceded the low-end for the time being it might as well be RISC-V that fills it. What's around certainly seems a better fit for low-power and mobile.
But the point is what's around. Sure, you don't hear as much about ARM, x86 or other projects at earlier stages, but that's also because the hype around RISC-V has encouraged a lot of people to make a lot of promises early that don't go anywhere (I mentioned Micro Magic for a reason). That can't be good for the ecosystem. Cores are only as good as the ones that make it to tape-out, and real engineers ship.