Fences are meant for serializing. Although the intel documentation says CPUID, you use a fence there. This should be obvious, as if you know what a fence is, you know they're entire purpose is serialization. I'll put what the manual says on them, but it's not a hard concept, the intel manualy literally says sfence = SERAILIZES STORES. Lfence = SERIALIZES LOADS. Mfence = SERIALIZES LOADS AND STORES. You clearly have ZERO idea what you're talking about if you don't even know what these simple instructions mean. So to answer your question in the quoted text, where it says to use a serializing instruction, it means to use the appropriate fence! Not only this, but your entire premise of a properly written getter/setter being "Wrong" is entirely wrong, as the entire reason for a race condition is having improper getters and setters!
Here are the following fences referenced in that article, and any good asm programmer will tell you that fences are used for this purpose(NOT CPUID)
LFENCE: (Intel manual Vol. 2A 3-585) *Description* Serializes load operations
Performs a serializing operation on all load-from-memory instructions that were issued prior the LFENCE instruction.
MFENCE: (Intel manual 4-22 Vol. 2B) *Description* Serializes load and store operations.
Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior
SFENCE:(4-620 Vol. 2B) Description: *Serializes* store operations
Orders processor execution relative to all memory stores prior to the SFENCE instruction. The processor ensures
that every store prior to SFENCE is globally visible before any store after SFENCE becomes globally visible. The
SFENCE instruction is ordered with respect to memory stores, other SFENCE instructions, MFENCE instructions,
and any serializing instructions (such as the CPUID instruction).
the MFENCE instruction.
I'm not sure what you think fences are, or what they're for. But they're clearly for serializing. And were talking about concurrency, that article is from the intel manual on multiprocessor programming, which is concurrency! Do you not even know basic terms? Do you not even read replies?
Please do not resort to personal attacks, we are just having a technical discussion.
In intel parlance 'serializing instruction' is a Word of Power; Please see Vol 3A, under serializing instructions. CPUID is listed there.
In the same section, LFENCE, MFENCE, SFENCE are listed as 'memory ordering instructions' and the documentation explicitly says that:
The following instructions are memory-ordering instructions, not serializing instructions. These drain the data memory subsystem. They do not serialize the instruction execution stream
Handling self modifying code requires serializing the instruction stream, so the memory fences are neither necessary nor sufficient[1].
Going back to the original argument, the memory fence instructions (and the various LOCK prefixed operations) do indeed serialize memory operations to guarantee ordering, which I don't dispute. But that's nothing to do with synchronizing caches like you claimed.
[1] IIRC MFENCE it is actually also a serializing instruction in practice, but Intel has not yet committed to document this behavior as architectural.
Here are the following fences referenced in that article, and any good asm programmer will tell you that fences are used for this purpose(NOT CPUID)
LFENCE: (Intel manual Vol. 2A 3-585) *Description* Serializes load operations Performs a serializing operation on all load-from-memory instructions that were issued prior the LFENCE instruction.
MFENCE: (Intel manual 4-22 Vol. 2B) *Description* Serializes load and store operations. Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior
SFENCE:(4-620 Vol. 2B) Description: *Serializes* store operations
Orders processor execution relative to all memory stores prior to the SFENCE instruction. The processor ensures that every store prior to SFENCE is globally visible before any store after SFENCE becomes globally visible. The SFENCE instruction is ordered with respect to memory stores, other SFENCE instructions, MFENCE instructions, and any serializing instructions (such as the CPUID instruction). the MFENCE instruction.
I'm not sure what you think fences are, or what they're for. But they're clearly for serializing. And were talking about concurrency, that article is from the intel manual on multiprocessor programming, which is concurrency! Do you not even know basic terms? Do you not even read replies?