A lot of wifi/other wireless analog devices go through analogous training procedures. Things like timing and delays are pretty important to these types of systems and you don't have a clock edge to synchronize against like you do in wired protocols like SPI (though I imagine DDR initialization does have pins used for this or similar).
Yeah, DDR does have a synchronous clock. One of the points of calibration is making sure the signals are actually sampled correctly wrt to the clock signal since the bit times are so short even small differences of trace length matter. The length matching is just to get it in the ballpark that can be corrected with per pin delays.
Ironically perhaps, at bit times like these it's easier to not have a clock signal and simply perform clock recovery like PCIe does, but that comes with higher latency for the interface.
