It's actually chisel. But github marks it as scala because chisel is based on scala.

Other HDL based on scala includes SpinalHDL.

These two HDL are pretty welcomed because of opensource and usability. You can find lots of projects in them. Notably rocket-chip, which is also in chisel. https://github.com/chipsalliance/rocket-chip

They're around for a while but still young and some people are pushing for adoption.

It is scala. Chisel is just a scala framework. Conceptually it's not quite an HDL but instead a scala program that metaprograms the actual RTL netlist. So there's no chisel compiler other than the standard scala one that comes with sbt; you then run the resulting chisel program on your computer to generate the netlist.

This is not strictly true anymore as the low-level (FIRRTL) compilation is powered by CIRCT (http://GitHub.com/llvm/circt) which is built using MLIR (part of the LLVM project: https://GitHub.com/llvm/llvm-project)

It's scala + a DSL called "chisel" that you write by chaining scala keywords and symbols in the right order.

There, solved it once and for all. :)

It's Chisel < https://www.chisel-lang.org/ > which runs on Scala and generates synthesizable Verilog for hardware implementation.

It was created and used by the same group that created RISC-V so it makes perfect sense.

SiFive, arguably the biggest player in RISC-V, use Chisel to design their processors.

Almost all of RISC-V is Scala land!

Scala has actually some stand in HW development and high-performance computing. See also https://spatial-lang.org/ which is another Scala DSL, this time for accelerators.

Scala in general is a much underrated language. One of the most powerful high level languages, but with a concise and very clean core. Since the new syntax was introduced in version 3 it even looks amazingly beautiful.

I know, people (frankly especially here on HN) are repeating some FUD about this language, but this are usually issues solved a decade ago.

People should really reconsider trying out Scala. Especially the new major version 3.

https://virtuslab.com/blog/the-most-common-scala-myths-debun...

This is a waste exaggeration. The Berkley people use Scala but just like everywhere else the majority of RISC-V is SystemVerilog and friends.

> Odd choice to do hardware design in scala...

Why? (I know nothing about hardware design, but know a thing or two about Scala. All the languages better than Scala are used even less than Scala.)