I've had this idea for a while: make an FPGA capable of executing WASM bytecode, then offloading WASM execution to the FPGA. Sounds like a fun project to learn FPGA and how to make a CPU.
Sorta off topic, but I wonder if a CPU with WASM bytecode as its native instruction set could be more performant / power-efficient than JIT-ing WASM code to ARM/x86 assembly. My understanding is that modern processors comes with a wide range of optimization tricks like register renaming, out-of-order, superscalar, ... such that it's probably just easier to JIT WASM bytecode to the native instruction set, so we'd get those optimizations for free, as opposed to design your own WASM CPU with those same optimizations.
Sorta off topic, but I wonder if a CPU with WASM bytecode as its native instruction set could be more performant / power-efficient than JIT-ing WASM code to ARM/x86 assembly. My understanding is that modern processors comes with a wide range of optimization tricks like register renaming, out-of-order, superscalar, ... such that it's probably just easier to JIT WASM bytecode to the native instruction set, so we'd get those optimizations for free, as opposed to design your own WASM CPU with those same optimizations.