On desktop, fast enough to run state-of-the-art games, decode 4k av1/h265 videos at 60fps (thread performance) without a 1kW power supply and water cooling. Since there will be a transition period before heavy assembly optimization starts to kick in (similar to dav1d decoder), would start with gcc/clang generated machine code. Oh, and should compile a full blown linux kernel and those horrible gcc/llvm as fast as their arm/x86_64 counter-parts. Compression/decompressing would be a good benchmark too.
Mobile: ratio power consumption/performance to run as smooth as the latest samsung galaxy flag ship the CPU-wise worst android apps, off AC.
Server: erf, I guess that would be tons of cores with tons of ram and cache then back to full blown linux kernel/gcc/llvm compilation speed&compression/decompressing&etc.
We are talking about world domination of a worldwide royalty free/ultra stable in time ISA (oxymoron).
I understood fast as to do with roadmaps, and used it that way.
Before year end for Veyron, next year for Ascalon. Potentially, there'll be further announcements for performant microarchitectures next year.
As for performance, with Ascalon promising similar to Zen5 performance at significantly reduced power consumption, I don't think there's much reason for concern: Very performant RISC-V microarchitectures are coming.
With all these companies and their strong teams working on new RISC-V microarchitectures, there'll be plenty of choice, soon.
I am always cautious about this. Very. You have those horrible compilers in the way.
I still dunno on which risc-v microarchitecture I'll start coding assembly (wanted to start on the mango mq pro something for a keyboard firmware 100% 64bits risc-v). Finally starting to get rid of those pesky compilers and system language syntax which are unable to be stable on the long run. At best, we'll get very high level language interpreter directly written in risc-v assembly. Just need to be very cautious about macro processor usage.
I started to code some core functions directly in x86_64, and I know it is only a transition phase towards risc-v 64bits ISA (porting from 1 modern ISA to another is still much, much, less work than to code from scratch). I'll enjoy the additional register space (even with a more register space consuming load/store ISA).
BTW, we still missing hardware instruction for direct memcpy/memset/memcmp in risc-v, that said I don't know if that will be pertinent in the end.
I would need mango pi mq pros I can buy with a noscript/basic (x)html browsers or a local retail shop, then time, a significant amount. I am currently on a biggy project which will take me months to wrap up (but it starts to get on my nerves... I might send it to hell)
Ofc, this firmware would be bare metal. Not jocking around. For the moment, I am a bit scared at porting to human assembly the SOC and board init code.
The only non-open source programs I know of are elf/linux video games and the steam client.
e.g. we know about Ventana Veyron, TBA before end of year, and Tenstorrent's Ascalon, TBA 2024, competitive with Zen5 which is also 2024.
Ascalon is 8-wide, but has smaller siblings at lesser decoder width, to cover a range of uses.
There's also Rivos, MIPS and SiFive working on very high performance cores, but we know less about these efforts.