Except that isn't true either except in the very narrow case of "front end for the sake of front end":
Lets say you have two, otherwise identical, use cases: You have the P and E Intel cores, and you have the equivalent over at AMD, Zen and Zen-c.
The respective E cores are approximately 50-60% of the size of their matching generation P cores, yet use about 40-50% of the power to get roughly the same performance (ie, 2x E cores vs a single P core with both threads running sometimes is comparable to each other, especially with all the anti-meltdown/spectre protections).
So, if you compare an P core, with two threads (which is 100% of the size of an P core, duh), or two E cores, each with a single thread, (which is 100% to 120% the size of that single P core), you have near equivalent performance often in less power usage.
If I consider the otherwise equivalency of a P core vs 2x E cores, the front end has widened (indeed, 2x E core has more frontend than 1x P core), and I have not significantly widened the backend (E cores from both companies are tiny, and only some of it can be contributed to less cache area).
I suspect AMD's end game is to eventually end dual-thread cores, and move to the model being done in Zen-c. One, it removes, forever, an entire class of possible security bugs (after all, Intel's knee-jerk reaction was to reissue series 8 as 9, with threads disabled and all cache assigned to first/only thread); two, it would make extremely high performance desktop and server chips that are better matched towards modern workloads; if AMD continues to make threaded cores, they will be 4/8 thread cores that are sold on specialty Epycs only (ie, the reverse of the current lineup of specialty Epycs being Zen4c, and no desktop Zen4c)
"But, hey, what about single-threaded-only workloads?" you might ask.
Workloads like that are generally memory latency bound first, memory bandwidth bound second, and then IPC bound third: AMD solved that by having an absolutely gigantic L3. Games are the poster-child of poorly optimized software, and AMD's giant L3 cache does magic here.
If my next chip was a 16c/16t E-core desktop chip (to replace your common 8c/16t, the kind I recommend to desktop users, and use myself), I'd be happy.
>> I suspect AMD's end game is to eventually end dual-thread cores
I think not. They're going to widen the fetch/decode in Zen 5. That will help refill the pipe after all those misprints and cache misses, but my not help latency in refilling. One of the best ways to handle stalls is to let "the other thread" execute. I suspect Zen 5 will get huge gains on branchy multi-threaded code but more modest gains on single thread. They're after performance per watt and per dollar, while Intel keeps aiming for top single thread performance and market segmentation - two things some of us don't care about.
That said, I'm sure there is a market for a 4 or 8 core chip without SMT that has 50 percent higher single thread performance, and I won't be surprised if Intel provides such a chip.
Lets say you have two, otherwise identical, use cases: You have the P and E Intel cores, and you have the equivalent over at AMD, Zen and Zen-c.
The respective E cores are approximately 50-60% of the size of their matching generation P cores, yet use about 40-50% of the power to get roughly the same performance (ie, 2x E cores vs a single P core with both threads running sometimes is comparable to each other, especially with all the anti-meltdown/spectre protections).
So, if you compare an P core, with two threads (which is 100% of the size of an P core, duh), or two E cores, each with a single thread, (which is 100% to 120% the size of that single P core), you have near equivalent performance often in less power usage.
If I consider the otherwise equivalency of a P core vs 2x E cores, the front end has widened (indeed, 2x E core has more frontend than 1x P core), and I have not significantly widened the backend (E cores from both companies are tiny, and only some of it can be contributed to less cache area).
I suspect AMD's end game is to eventually end dual-thread cores, and move to the model being done in Zen-c. One, it removes, forever, an entire class of possible security bugs (after all, Intel's knee-jerk reaction was to reissue series 8 as 9, with threads disabled and all cache assigned to first/only thread); two, it would make extremely high performance desktop and server chips that are better matched towards modern workloads; if AMD continues to make threaded cores, they will be 4/8 thread cores that are sold on specialty Epycs only (ie, the reverse of the current lineup of specialty Epycs being Zen4c, and no desktop Zen4c)
"But, hey, what about single-threaded-only workloads?" you might ask.
Workloads like that are generally memory latency bound first, memory bandwidth bound second, and then IPC bound third: AMD solved that by having an absolutely gigantic L3. Games are the poster-child of poorly optimized software, and AMD's giant L3 cache does magic here.
If my next chip was a 16c/16t E-core desktop chip (to replace your common 8c/16t, the kind I recommend to desktop users, and use myself), I'd be happy.