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Also looks like PCIe is exposed via an FPC connector. You could probably come up with a scheme to have an M2 device mounted behind the board - if you really wanted.

Only having a single lane of PCIe 2.0 is a little unfortunate. I wonder if the inevitable compute module will get more or not. It seems that their IO chip is also attached via PCIe but it provides a lot of the interfaces that you’d expect to have - so my hunch is that it’ll be included on any CM5.



it can be forces into "experimental" 3.0 mode so thats something.




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