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If it's desired integer performance could far exceed float performance, since ALUs need less die area than FPUs.

If this paper holds, I'd expect that's where custom accelerators will be heading.



Oh, I agree, I'm just saying that there is no reason in principle for floats performance to be better than integer.

edit: also this might be implementable purely using bitwise vector operations. Would need to check the throughput of those.




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