Registers and ALUs are sort of already coupled like that in practice.
Longer, less wrong version: modern CPUs have forwarding networks with latches in them. Those latches store ALU results. Those results are (usually) the equivalent of the content-to-be of a specific version of a register -- and by register, I actually mean register name.
So, "registers" that are currently active get to live in the forwarding network where all the routing is and "registers" that aren't as active get to live in the register file, away from the ALUs and the forwarding network.
(And the "registers" used in machine instructions are really just register names. There's a lot renaming going on in order to keep many versions (and potential versions) of register values live at the same time to enable superscalar execution and out-of-order execution.)
Longer, less wrong version: modern CPUs have forwarding networks with latches in them. Those latches store ALU results. Those results are (usually) the equivalent of the content-to-be of a specific version of a register -- and by register, I actually mean register name.
So, "registers" that are currently active get to live in the forwarding network where all the routing is and "registers" that aren't as active get to live in the register file, away from the ALUs and the forwarding network.
(And the "registers" used in machine instructions are really just register names. There's a lot renaming going on in order to keep many versions (and potential versions) of register values live at the same time to enable superscalar execution and out-of-order execution.)