Compile same code for aarch64 and riscv64. Compare.

It is well known design deficiency. Much like lack of bit field ops.

Do you have code examples for this? I'm looking for cases where RISC-V is lacking compared to arm.

Sounds extremely subjective.

i.e. it does not have my favored instructions or addressing modes, so it must be worse.

You’re replying to the author of the post explaining why he would have to do more in software to emulate RISC-V than MIPS and that would be more effort and run slower, and you’re telling him “that’s extremely subjective”?

How is that subjective?

"well known design deficiency" is the subjective part.

Much like juggling with your feet instead of hands is subjectively worse.

From a hardware perspective, juggling is better without flags and without unnecessary addressing modes.

Neither are concepts RISC-V invented, but rather, adopted. Ideas that have been plenty tested out there, and proven beneficial.

Large body of evidence trumps intuition and guesswork. Most of this is documented in the spec itself and/or in:

Computer Architecture: A Quantitative Approach (John L. Hennessy, David A. Patterson)

I just meant that it's somewhat unergonomic when dealing with the instruction set directly, FWIW. Thanks for the reference.