> What did I say[0]? I said you can't explain everything by the increasing die size. And added information that scaling is a non-trivial technological challenge than your previous comments suggest.
Scaling is a non-trivial challenge, but that doesn't mean the "Moore's Law" rate of progress is being kept up, or rather it isn't if you treat it as a way to track transistor density. In other words, I don't deny that progress is still being made, but the Moore's Law speed of progress is not.
As for die size not accounting for everything, I've already explained that it doesn't account for everything, but it does account for a large part in perceived technical progress. If you think about it it's quite simple, if the rate of transistor shrinkage has decreased in real physical terms (not in the "5nm", "3nm", etc... marketing terms), there's only a few different ways that can happen and you still end up with chips with a larger number of transistors...
1. You can build out vertically, i.e. stacking multiple transistor layers.
2. You can build out horizontally, i.e. increase the width of the die size.
3. You can try to optimise routing or remove non-transistor components from the chips to free up room.
All three are valid options, but they're not equal in terms of achieving a large boost in transistor count. Option 1 is being worked on and is likely to be more of a feature in upcoming process nodes. Option 3 is useful but limited, in the sense that the routing for these chips is already strongly optimised, and unless you couple it with Option 1 the scope for improvements are limited. This leaves you with Option 2, which is both the easiest and cheapest to achieve with current technology.
With these factors in mind, it's obvious that a large part of how transistor counts keep going up with a slowed rate of improvement in transistor size is going to be through increasing die size.
To help illustrate the point further, take a look at this table of Nvidia GPU die sizes. Note that although the growth is not linear, there is a clear trend towards larger die sizes over time.
Scaling is a non-trivial challenge, but that doesn't mean the "Moore's Law" rate of progress is being kept up, or rather it isn't if you treat it as a way to track transistor density. In other words, I don't deny that progress is still being made, but the Moore's Law speed of progress is not.
As for die size not accounting for everything, I've already explained that it doesn't account for everything, but it does account for a large part in perceived technical progress. If you think about it it's quite simple, if the rate of transistor shrinkage has decreased in real physical terms (not in the "5nm", "3nm", etc... marketing terms), there's only a few different ways that can happen and you still end up with chips with a larger number of transistors...
1. You can build out vertically, i.e. stacking multiple transistor layers.
2. You can build out horizontally, i.e. increase the width of the die size.
3. You can try to optimise routing or remove non-transistor components from the chips to free up room.
All three are valid options, but they're not equal in terms of achieving a large boost in transistor count. Option 1 is being worked on and is likely to be more of a feature in upcoming process nodes. Option 3 is useful but limited, in the sense that the routing for these chips is already strongly optimised, and unless you couple it with Option 1 the scope for improvements are limited. This leaves you with Option 2, which is both the easiest and cheapest to achieve with current technology.
With these factors in mind, it's obvious that a large part of how transistor counts keep going up with a slowed rate of improvement in transistor size is going to be through increasing die size.
To help illustrate the point further, take a look at this table of Nvidia GPU die sizes. Note that although the growth is not linear, there is a clear trend towards larger die sizes over time.
https://www.techpowerup.com/forums/threads/major-nvidia-die-...