Hi Andrew, great overview looking at the foundations of programmable logic. I recognize the look of the schematics from CircuitLab! Noticed that you went out of your way to take screenshots -- is there something we can do to make it easier to use our image export, or alternatively some sort of embeddable widget like you use for the Verilog gists?

Hey Mike! Cool to see circuitlab developer(s?) on HN! It's an awesome tool.

When writing these blog posts, I usually create a single circuit with a bunch of disparate parts - I don't need the circuit to be functional for any simulation purposes, I just need the diagrams and rendering. Part of the reason that I only use a single circuit is that I need to copy and paste different parts, and I'm not sure if copying/pasting between different circuits is possible. Also, copy/paste rather often dies on me, especially when selecting multiple components, which makes workflow a bit more complicated. (This happens to me rather often and is really annoying, because the only way to fix it is to close the tab and restart. Symptoms after breakage include inability to copy/paste or move any circuit elements around. If there's any way to submit debug logs for when this happens, feel free to let me know and I'll be sure to try next time it happens. You have my email.)

Exporting via the export tool produces a single PNG file for the entire circuit, where I often need just a bit of the entire diagram. Screenshots let me select a small portion of the circuit.

I'm not entirely sure how this could be fixed. If there were gist-like embeddable widgets, I think the convenience of those would outweigh the disadvantages of a slightly different workflow. Circuit "gists" would be awesome. Another thing that would be great is if I could select a bunch of elements on a circuit, click on some button, and have a new circuit created with only those elements in it. (Note that I'm just brainstorming what would help me specifically, so I don't know how all this might fit into your product.)

Anyway, CircuitLab is awesome! Thanks for making it.

Excellent -- we've been thinking about this a lot on our end, and we'll be in touch via e-mail. Copy/paste between browser tabs/windows does work (uses HTML5 localStorage), but it sounds like you might be having a different issue and we'll follow up. Thanks!

Hey, another user here that would love to be able to just export parts of the circuit. I usually just use circuitlab for the rendering because SPICE is ugly and bloated and when in need of good looking schematics for reports circuitlab is great.

Maybe have a tool that allows you to select just a part of the schematic like some print screen tools have when you just want to save a part of the screen, and export just that. I never experienced the crashes that the other poster talks about though.

Thanks for a great product by the way!

Didn't expect to see Verilog on the front page of HN.

1 nit pick, I think wherever you use a wire assignment you need the assign keyword. e.g

  wire [1:0] command = mem_out[7:6];
  wire [2:0] destination_addr = mem_out[6:3];
  wire [2:0] source_addr = mem_out[2:0];

should be

  assign wire [1:0] command = mem_out[7:6];
  assign wire [2:0] destination_addr = mem_out[6:3];
  assign wire [2:0] source_addr = mem_out[2:0];

Or maybe it's wire assign. I usually first declare the wire in a single statement then use assign on a new line.

Could this be dependent on the Verilog version? At the very least, the wire assignments without the 'assign' keyword seem to work in the iverilog simulator as well as Altera's Quartus suite synthesis tools. I have seen both conventions (wire declaration and assignment separately or together), but I believe the assign keyword is only required for the former.

For future reference (since I can't edit): I spent a while researching and couldn't find any definitive answer, but found some places which supported the implicit assignment ([0], [1]). However, these aren't anything official, so I think ultimately it just depends on what your particular implementation supports...

[0] http://www.verilogtutorial.info/chapter_2.htm [1] http://www.doulos.com/knowhow/verilog_designers_guide/wire_a...

You're right. I just tested it in Xilinx ISE 13.4 and it seemed to work without using any assign as both a single wire and a bus. I just recall seeing an error message at some point in the past which was about something similar.

I took a quick look at the IEEE 1800-2009 LRM (SystemVerilog, a proper superset of Verilog), and I can't see any BNF production that allows this. I think this is a case of iverilog being somewhat permissive.

In looking it up, I did come across the keyword "alias", which I was not familiar with, that effectively does what you've done here.

That said, it doesn't detract from an enjoyable tutorial. It's nice to see a little ASIC content on HN - duly upvoted!

Thanks! Nice to know. I must've picked the habit up before from just reading code on the internet (as per my other comment in this thread), but I'll try to phase this out. This is what I love about Hacker News - people commenting really know their stuff, almost always well enough to teach me something :)

Well, apparently I don't know what I'm talking about at all - it does work in the 3 major simulators. Typo in my code. Ooops.

It appears to be valid, and does not require "assign".

This is what I like about HN - smart people keeping me on my toes!

Assigning the wire on the same line it is declared is supported in all major synthesis and simulation tools I have used. I'm not sure what verilog standard its from, but I would guess its part of verilog 2001.

A good resource on this same subject is the book 'Code' by Charles Petzold. It is also a bottom up approach to understanding computers.

A very good introduction to how a computer works from the inside, but you need to know the syntax of Verilog to really understand the code you wrote, any way it gives a general feel to people outside the VHDL domain, like me who is a systems integrator and designer I work at a 30,000 feet view on assembly upto C, C++, PHP and DotNet.

My first processor was a Z80! :)

I did z80 on TRS-80 Model 1's and 6809 on the TRS-80 Color Computer.

They were not very complicated machines and thus made it easier to create assembly language programs that actually did stuff you could observe quickly. I think the fast feedback loop between coding in assembly and having observable results (i.e. graphics etc.) made for a nice learning platform.

http://en.wikipedia.org/wiki/TRS-80_Color_Computer http://en.wikipedia.org/wiki/TRS-80#The_Model_I

I think today's processors are very cool but trying to teach someone assembly on a monster like the modern processors and having to do all sorts of things to try and flip a single bit on the screen via GPU's etc. makes for a rough learning experience. I notice very few college programs are doing low level courses and I think it impacts the students in very subtle but real ways that creep into code because of their lack of the low-level details of how computers work.

...and I remember a third of the Z80 machine code space. It was in octal - 2-bit operation, 3-bit destination,, 3-bit source. Registers were numbered b,c,d,e,h,l,m,a. So 377 would be move a,a which was a noop.

'm' was 'indirect thru h:l' so it did a 16-bit address fetch or store.