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One of the more interesting bits of speculation about the design's motivations that I've seen so far is an anonymous comment on the Slashdot version of this story: http://hardware.slashdot.org/comments.pl?sid=5519563&cid=476...



This is another good post, despite the appeal to authority: http://hardware.slashdot.org/comments.pl?sid=5519563&cid=476...

Saying "When an in-order CPU stalls on memory, it's still burning power while waiting, while an OOO processor is still getting work done" seems deceptive, though. The OOO processor is (often) doing speculative work, which may be unneeded, and a stalled in-order CPU won't be using quite the same amount of power as if the execution units were actually switching.

Though I'm pretty sure the NVIDIA design must speculative prefetch and hoist memory reads aggressively to be performance competitive (see the huge cache sizes!), which also burns power.




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