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The Colwell paper really is excellent. And given feature sizes of chips today it would be fascinating to see a 432 implemented as envisioned, rather than as possible given transistor counts of the day. It was going to be the microprocessor version of the MULTICs system and much of what it imagined doing in hardware (capabilities) would make for secure environments that you could reason about more effectively. Probably make for a great FPGA project now.



Thank you! Those are awesome. Downloaded all the papers to my iPad for perusal.


This is the newest (and my favourite) paper http://www.csl.sri.com/users/neumann/2015oak.pdf

Another chip that is better supporting privilege separation (but not using Capability-based addressing) is the Mill. (disclosure: I'm on the Mill team).


lowRISC (an open SoC effort for the RISC-V arch) has a form of tagged memory, that among other things can be used for capabilities.

[0] http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-... [1] http://www.lowrisc.org/blog/2015/04/lowrisc-tagged-memory-pr...




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