No they aren't internally RISC. On big Intel & AMD cores "ADD reg, mem" translates to a single uop. On Intel Atom even "ADD mem, reg" translates to a single uop. In fact, it is mostly legacy instructions (e.g. binary-coded decimal arithmetic) that are translated into multiple uops.
x86 uops are very wide, much wider than RISC instructions and more like VLIWs; P6 uops are 118 bits and I haven't easily found any description of the newer models but they are likely even wider.
