The switch to FinFET is already a use of the 3rd dimension. The channel is moved vertically to reduce the surface area of the transistor. GAAFET are also using the 3rd dimension.
But these are uses of the 3rd dimension within the transistor.
You are probably talking about a more global use of the 3rd dimension.
CFET technology is envisaged to exploit the 3rd dimension within logic cells. The idea is to stack the N-type transistors on top of the P-type transistors to save surface area.
But you are probably talking about an even more global use of the 3rd dimension. Where the idea would be something like stacking logic cells.
However, this will cause power supply and heat dissipation issues.
Nowadays companies are trying to bring the power supply from the bottom of the transistor (so-called buried power rail) to leave more room on top for routing. If you start stacking logic gates, where should the power flows?
How much heat can you move from the center of the chip using conductors?
I supposed it’s a bit like elevators though. As you make the chip taller the real estate for transport goes up until the entire volume is dedicated to transportation.
That's a good question ! But I can't give you a accurate answer.
In my post I didn't elaborate on thermal dissipation issues because I think there are already enough problems with geometry and routing.
But heat dissipation is already a concern today, even before increasing the number of transistor layers.
If in a modern chip all the transistors were active simultaneously at high frequency, then the chip would probably be destroyed instantly due to overheating.
This is called the "Power Wall", which limits the frequency and (active) transistor density.
In a modern circuit it is common for one part of the circuit not to be active simultaneously with an adjacent one in order to avoid overheating.
It is also common to place blocks based on whether or not they are likely to be active at the same time.
It's common to have logic only used for factory testing. (design for testability (DFT) and design for manufacturing (DFM))
It is also common to add logic cells connected to nothing which can be repurposed in case a bug is found in the hardware and we need to fix it without replacing all the manufacturing masks, which would cost millions of dollars. (which is called spare cell insertion)
All this constitutes what is called the darksilicon.
In the case of a 2D circuit, all the transistors are exposed to heat dissipation in approximately the same way.
Now imagine the same problems, but in 3D, and adding the idea that some cells, in the center, can dissipate less heat than those near the surface. It must be a nightmare.
However, there is a potential solution to this problem: nanofluidics cooling.
It seems when we have these conversations that people bring up the capacitive and inductive liabilities of having a large chunk of electrically conductive material near a circuit. Chunks of copper 'cost' more than lost real estate. Nobody has done that yet in this thread so I might as well volunteer it.
There are materials that are electrical insulators but not thermal insulators, but I don't know how you put them into a chip. How long before we circle back to chips made of synthetic diamond?
Also as you stack the chip features deeper, does the variability in thermal expansion of all of the materials start to cause bigger and bigger problems? Is that an unspoken assumption under the umbrella of "moving heat from the middle of the chip"? I've seen midwestern roads after a hard winter and a hot summer. Thermal cycling can be brutal.
Oh yeah, it's a problem: both of Intel's big recent process holdups (cobalt wires, contact over active gate) almost certainly happened because thermal cycling caused more problems than expected from pre-production tests.
> The best design they found is able to handle heat fluxes up to 1,700 watts per square centimeter.
This was not a 3-dimensional chip, of course, but it might give a ballpark figure for the heat transfer we could achieve with nanofluidics. The article and paper authors take care to point out that this was effectively a "toy" example, with the circuit designed to be easy to cool.
Tiny chip, HUUUUGE heatsink. Assuming a similar chip size to what we currently use that would be 3.4kW of heat you need to dissipate from a tiny 2cm^2 contact patch. Some sort of liquid cooling would probably be necessary, just to move the heat fast enough to avoid melting the package.
But these are uses of the 3rd dimension within the transistor.
You are probably talking about a more global use of the 3rd dimension.
CFET technology is envisaged to exploit the 3rd dimension within logic cells. The idea is to stack the N-type transistors on top of the P-type transistors to save surface area.
But you are probably talking about an even more global use of the 3rd dimension. Where the idea would be something like stacking logic cells.
However, this will cause power supply and heat dissipation issues. Nowadays companies are trying to bring the power supply from the bottom of the transistor (so-called buried power rail) to leave more room on top for routing. If you start stacking logic gates, where should the power flows?