Are there any [serious] attempts to go three dimensional? And I do not mean stacking a couple of dies, I mean building inside a volume with dimensions and densities in all three dimensions comparable to what we are currently doing in two dimensions.
If one naively considers going from transistors of area a² on dies of area b² to transistors of volume a³ in a three dimensional die of volume b³, one finds that we could have quadrillions of transistors in a cube with side lengths of tens of millimetres using currently available transistor sizes. It would of course instantly melt itself due to the different scaling behaviors of different quantities.
But we can reduce transistor area only so much until we end up at the size of molecular or single atom transistors, we are currently probably on the order of hundred atoms side length.
The switch to FinFET is already a use of the 3rd dimension. The channel is moved vertically to reduce the surface area of the transistor. GAAFET are also using the 3rd dimension.
But these are uses of the 3rd dimension within the transistor.
You are probably talking about a more global use of the 3rd dimension.
CFET technology is envisaged to exploit the 3rd dimension within logic cells. The idea is to stack the N-type transistors on top of the P-type transistors to save surface area.
But you are probably talking about an even more global use of the 3rd dimension. Where the idea would be something like stacking logic cells.
However, this will cause power supply and heat dissipation issues.
Nowadays companies are trying to bring the power supply from the bottom of the transistor (so-called buried power rail) to leave more room on top for routing. If you start stacking logic gates, where should the power flows?
How much heat can you move from the center of the chip using conductors?
I supposed it’s a bit like elevators though. As you make the chip taller the real estate for transport goes up until the entire volume is dedicated to transportation.
That's a good question ! But I can't give you a accurate answer.
In my post I didn't elaborate on thermal dissipation issues because I think there are already enough problems with geometry and routing.
But heat dissipation is already a concern today, even before increasing the number of transistor layers.
If in a modern chip all the transistors were active simultaneously at high frequency, then the chip would probably be destroyed instantly due to overheating.
This is called the "Power Wall", which limits the frequency and (active) transistor density.
In a modern circuit it is common for one part of the circuit not to be active simultaneously with an adjacent one in order to avoid overheating.
It is also common to place blocks based on whether or not they are likely to be active at the same time.
It's common to have logic only used for factory testing. (design for testability (DFT) and design for manufacturing (DFM))
It is also common to add logic cells connected to nothing which can be repurposed in case a bug is found in the hardware and we need to fix it without replacing all the manufacturing masks, which would cost millions of dollars. (which is called spare cell insertion)
All this constitutes what is called the darksilicon.
In the case of a 2D circuit, all the transistors are exposed to heat dissipation in approximately the same way.
Now imagine the same problems, but in 3D, and adding the idea that some cells, in the center, can dissipate less heat than those near the surface. It must be a nightmare.
However, there is a potential solution to this problem: nanofluidics cooling.
It seems when we have these conversations that people bring up the capacitive and inductive liabilities of having a large chunk of electrically conductive material near a circuit. Chunks of copper 'cost' more than lost real estate. Nobody has done that yet in this thread so I might as well volunteer it.
There are materials that are electrical insulators but not thermal insulators, but I don't know how you put them into a chip. How long before we circle back to chips made of synthetic diamond?
Also as you stack the chip features deeper, does the variability in thermal expansion of all of the materials start to cause bigger and bigger problems? Is that an unspoken assumption under the umbrella of "moving heat from the middle of the chip"? I've seen midwestern roads after a hard winter and a hot summer. Thermal cycling can be brutal.
Oh yeah, it's a problem: both of Intel's big recent process holdups (cobalt wires, contact over active gate) almost certainly happened because thermal cycling caused more problems than expected from pre-production tests.
> The best design they found is able to handle heat fluxes up to 1,700 watts per square centimeter.
This was not a 3-dimensional chip, of course, but it might give a ballpark figure for the heat transfer we could achieve with nanofluidics. The article and paper authors take care to point out that this was effectively a "toy" example, with the circuit designed to be easy to cool.
Tiny chip, HUUUUGE heatsink. Assuming a similar chip size to what we currently use that would be 3.4kW of heat you need to dissipate from a tiny 2cm^2 contact patch. Some sort of liquid cooling would probably be necessary, just to move the heat fast enough to avoid melting the package.
There are a number of full-3D designs in the works today. The challenge has been thermal dissipation, and as long as it's not logic-on-logic, it works. So that becomes a placement challenge, and EDA tools are still catching up. But there are some interesting new approaches out there, too. TSMC has figured out a way to stack chiplets inside a chip. So rather than going up, it's going down. They say that approach solves the thermal issues because the silicon acts as a heat sink. Here's a story that explains it: https://semiengineering.com/momentum-builds-for-advanced-pac... (Scroll down to the SoIC stuff under TSMC). The front-end packaging is new, meaning it's done at the front end of the manufacturing process. More work is being done the traditional way, too, whether it's pillars rising up off a substrate, or die on die (or die on die on die).
There are various areas. 3DNAND is a fully 3D design, and scaled reasonably past the limits of 2D. Crosspoint memory is a simplified 3D structure.
In logic, people (Unity, for instance) talk about fully 3D, with stacks of transistors layered. This turns out to be capability and thermally limited.
The most interesting variant today are the N over P nanosheets. Instead of having N and P transistors next to each other, putting them on top saves area. Contact and interconnect are still limiting, but this gives a node shrink without lateral shrink.
It isn't completely obvious to me that this gives enough design flexibility to be worth it, but maybe?
So anyway, there are good attempts, and the stacked NPN is the most likely.
(Arrgh. They redesigned their already bad website into something even more bad)
There were some talks at semiconductor fabbing conferences with them, some presentations directly from them on youtube, some papers, some press(very little) over the past years.
I've seen no implementations, samples, not even prototypes so far. No design wins either. All theoretical. But seems plausible to me. So does vaporware.
At least they have an office address almost next to intel in Oregon :)
Stacked silicon is a thing, DRAM is already stacked 32 or even 64 layers, but for logic chips even those are being stacked - HBM can be a memory die stacked on a logic die, and there are so called 3d-ICs which can stack either active on active or active on passive dies. The next step would be more than 2 dies stacked, but that will have some interesting heat dissipation challenges...
Historically, each layer of circuits could have a flaws and so yield would drop per layer. With chiplet packaging you might be able to stack some of the chips vertically, if you can handle that much heat.
So for instance how much could you scale performance of a mobile chip by adding more transistors vertically until it has close to the same power draw as a desktop chip?
Memory devices are already fully 3D. DRAM has been using stacked capacitors for more than 10 years, where the logic is on the wafer surface but the storage capacitors are built up onto the fully processed wafer.
3D NAND (VNAND) is also fully vertical -- again, the logic is all on the wafer surface but the storage cells are built up.
I can't say I have a great deal of knowledge on the subject, but isn't doping done by surface diffusion? How would the transistors be created in the interior of the volume?
I do not think this would be practical but at least in principle one could build 10,000 by 10,000 transistors in a layer, deposit some material on top, and then start building the next layer. Repeat 10,000 times. When you are done, you would have a cube of maybe about 2 mm side length containing a trillion transistors.
It would be somewhat like 3D printing, you repeat a fundamentally two dimensional process along a third dimension over and over again. And to some extend this is exactly how chips are currently made, in many steps and layers to build up the different transistor parts and the interconnect.
But it could certainly be the case that this is not practical and one would have to look for fundamentally different processes to build up such structures, maybe some self-assembly process. But I really have no clue if and what has been considered, that is why I asked about it in the first place.
The reason this is not done is that you want the channel of your transistors to consist of a fully epitaxial layer (that is, an entirely clean and regular lattice of atoms) of silicon for best performance. It's not possible to deposit such layers, they are only formed during crystal formation when the silicon ingot is formed.
3d-nand is built sort of like you propose (except that instead of 10000 vertically stacked layers, they are up to a few hundred), but they get away with using sucky polysilicon for their channel because only a very small part of the chip is ever lit at the same time, so it's okay for the channels to leak like a sieve.
Well, many CPU designs are made so that a few defects can be worked around at the cost of a bit of performance. It might be possible to do something like that and include a few spare logic units on each layer to get a decent yield.
I'm going off topic a bit here, but it's something I've thought of before...
We're at the point where single-core performance gains on each generation are weak, and instead are now heading for massive parallelization. Is the the speed of light (more specifically, the speed of current) actually the limiting factor here?
At 5 Ghz, in the time it takes for the clock to tick once, light travels 6 cm (2.36 inches). I know electrical current moves even slower than that (and varies depending on the material), so is it possible that it could impact theoretical maximum performance per core, at least limiting clock speeds, due to signals going across the CPU and across components being out of sync?
Speed of memory has been the bottleneck all along. More transistors are only useful if they are L1 cache, but to take advantage of larger caches we need to change the OS/languages we use. I would say 1 Gflops/Watt is peak 32-bit CPU, I think most people should try and work from that number and keep energy usage as low as possible. Raspberry 4 for desktop! 28nm is enough, going smaller creates more problems than it solves.
We can make memory 10x faster for 20x the price, but most devices barely need it at 0.5x the current speed so there's no demand to drag that price down.
Synchronizing clock domains is already an issue. More commonly a problem in FPGAs (larger dies, more buffering & switching, so slower clock traversal across a larger distance), but it definitely has to be accounted for in CPU design.
> At each node, process cost and complexity are skyrocketing, so now the cadence for a fully scaled node has extended from 18 months to 2.5 years or longer. In addition, fewer foundry customers can afford to move to advanced nodes.
So of course let's not even mention any technology beyond silicon photolithography.
They mention a 1.5nm process node, which is 7.5 silicon atoms wide. So: A) why aren't we talking about 1.4 or 1.6 nm instead? And B) at what point will the industry acknowledge the need for atomically precise manufacturing?
The process name doesn’t have anything to do with the physical dimensions of the transistor. It’s a marketing term, a lower number implying a newer node.
Besides, using one metric to measure a 3D object wouldn’t make too much sense, at least in the case of a FinFET transistor. A more useful metric would be transistor density.
> The process name doesn’t have anything to do with the physical dimensions of the transistor. It’s a marketing term, a lower number implying a newer node.
It seems I'm definitely in grumpy old man territory these days when things like the process node name which used to actually mean something specific, don't anymore.
It still means something specific. It's an extrapolation of the transistor density. The design rules on state of the art processes are too complex to summarize with a simple single number like in days past, so this is a reasonable way to describe things. The argument that they're purely meaningless marketing numbers is just tired empty smugness. When we talk about TSMC 7nm everyone knows what that means and that it is indeed a significant advance over the prior nodes. The numbers capture the advantage in rough terms, as best you can.
Yeah, I’m with you having worked in a fab for a short time.
But... it assumed all other things related to structure and configuration etc remained the same. That hasn’t been true for a while and so now it’s “10nm equivalent” shortened to 10n. Can’t remember when that started to change... maybe at 280?
I dont blame them. Some company made the first claim, others try to resist. Then customers demand a new node for their marketing.... and that is how we end up with these numbers.
Selective growth and patterning already have precision in the sub angstrom range, over mms of distance. This is what 'TMU' is, when you read an ASML or Lam paper on the topic. Current target is sub nm, for total variation cross die per layer.
I strongly recommend a read of the Tennant's law series onnlithoguru, or Tim Brunner's paper on why optical lithography wins forever.in short, optical is better (including EUV).
There are whole conferences dedicated to atomically precise manufactue, and hundreds of not thousands of people working in the field.
If one naively considers going from transistors of area a² on dies of area b² to transistors of volume a³ in a three dimensional die of volume b³, one finds that we could have quadrillions of transistors in a cube with side lengths of tens of millimetres using currently available transistor sizes. It would of course instantly melt itself due to the different scaling behaviors of different quantities.
But we can reduce transistor area only so much until we end up at the size of molecular or single atom transistors, we are currently probably on the order of hundred atoms side length.