It is probably not right to say that BiiN was in any way a follow on the iAPX432.
It might have inherited a few ideas from iAPX432 and maybe also some designers, but otherwise it was a very different architecture, whose development was obviously triggered by the much publicity about the RISC advantages. At the same time, most companies involved in computers had concurrent RISC development programs, e.g. IBM, ARM, HP, AMD, Motorola, Fairchild, DEC.
I have not seen yet any document that would explain why Siemens has joined Intel into the BiiN project, what was Siemens expecting from the project and how the Intel and Siemens contributions to the project were split.
In any case, in 1988 Siemens has chosen to exit the BiiN project leaving Intel as its sole owner.
After renaming BiiN to 80960 (Intel had an 8096 series of 16-bit microcontrollers, which were supposed to be replaced by 80960), Intel has introduced the first 2 products based on it before the end of 1988, and in 1989 they have introduced additional variants.
80960 included many innovations, they were the first RISC ISA designed by Intel and already the 1988 products have been the first monolithic CPUs having the atomic fetch-and-add instruction (which had been invented in 1980/1981 for the NYU Ultracomputer project). The atomic fetch-and-add instruction was later included in the Intel 80486 instruction set (with the mnemonic XADD).
One of the 80960 variants introduced in 1989 (80960CA) was the first monolithic superscalar CPU, one year before IBM POWER. The first superscalar design had been the IBM ACS research project (1966), but the word "superscalar" has been coined only in 1987, by the team designing IBM POWER. In this case Intel has been very quick to include the results of published research in their design, even quicker than those who published them (but obviously, IBM POWER was a far more ambitious project, with CPUs for scientific workstations having a much higher performance than 80960CA).
After learning how to implement them in 80960, the more important innovations have been included by Intel in their mainstream CPUs, 80486, then Pentium (first mainstream superscalar).
While the 432 was a memory-to-memory CISC and the 960 a classic RISC, I do think they have a lot in common technically. A key difference is that the 432 uses positive/negative offsets to separate raw data and capabilities while the 960 had an optional bit 33 to do the same thing, which makes it far simpler to mix data and capabilities on the stack.
The "operating in hardware" is microcode in the 432 but RISC-friendly in the 960, but it is still there.
I am talking about the original 960MX here. Most of these features were dropped on the following 960 models, if I understood correctly. Those do not indeed have much in common with the 432.
I agree that the mechanism of implementing memory protection by capabilities was inherited by BiiN from iAPX432, but as you have said, after Intel has renamed BiiN to 80960 and they have changed its intended market from general-purpose CPUs to 32-bit microcontrollers, competing there with the older 16-bit MCUs or with 32-bit MCUs like AMD 29000, such high-level features have been dropped.
Nowadays there are attempts to resurrect the use of the memory tagging method for memory protection, e.g. the Cambridge CHERI research project, which has been implemented by ARM in their Morello demonstrator board.
Like the original BiiN/80960, CHERI uses an 1-bit memory tag for each 128 memory bits, to differentiate raw memory from capabilities.
It might have inherited a few ideas from iAPX432 and maybe also some designers, but otherwise it was a very different architecture, whose development was obviously triggered by the much publicity about the RISC advantages. At the same time, most companies involved in computers had concurrent RISC development programs, e.g. IBM, ARM, HP, AMD, Motorola, Fairchild, DEC.
I have not seen yet any document that would explain why Siemens has joined Intel into the BiiN project, what was Siemens expecting from the project and how the Intel and Siemens contributions to the project were split.
In any case, in 1988 Siemens has chosen to exit the BiiN project leaving Intel as its sole owner.
After renaming BiiN to 80960 (Intel had an 8096 series of 16-bit microcontrollers, which were supposed to be replaced by 80960), Intel has introduced the first 2 products based on it before the end of 1988, and in 1989 they have introduced additional variants.
80960 included many innovations, they were the first RISC ISA designed by Intel and already the 1988 products have been the first monolithic CPUs having the atomic fetch-and-add instruction (which had been invented in 1980/1981 for the NYU Ultracomputer project). The atomic fetch-and-add instruction was later included in the Intel 80486 instruction set (with the mnemonic XADD).
One of the 80960 variants introduced in 1989 (80960CA) was the first monolithic superscalar CPU, one year before IBM POWER. The first superscalar design had been the IBM ACS research project (1966), but the word "superscalar" has been coined only in 1987, by the team designing IBM POWER. In this case Intel has been very quick to include the results of published research in their design, even quicker than those who published them (but obviously, IBM POWER was a far more ambitious project, with CPUs for scientific workstations having a much higher performance than 80960CA).
After learning how to implement them in 80960, the more important innovations have been included by Intel in their mainstream CPUs, 80486, then Pentium (first mainstream superscalar).