While the 432 was a memory-to-memory CISC and the 960 a classic RISC, I do think they have a lot in common technically. A key difference is that the 432 uses positive/negative offsets to separate raw data and capabilities while the 960 had an optional bit 33 to do the same thing, which makes it far simpler to mix data and capabilities on the stack.
The "operating in hardware" is microcode in the 432 but RISC-friendly in the 960, but it is still there.
I am talking about the original 960MX here. Most of these features were dropped on the following 960 models, if I understood correctly. Those do not indeed have much in common with the 432.
I agree that the mechanism of implementing memory protection by capabilities was inherited by BiiN from iAPX432, but as you have said, after Intel has renamed BiiN to 80960 and they have changed its intended market from general-purpose CPUs to 32-bit microcontrollers, competing there with the older 16-bit MCUs or with 32-bit MCUs like AMD 29000, such high-level features have been dropped.
Nowadays there are attempts to resurrect the use of the memory tagging method for memory protection, e.g. the Cambridge CHERI research project, which has been implemented by ARM in their Morello demonstrator board.
Like the original BiiN/80960, CHERI uses an 1-bit memory tag for each 128 memory bits, to differentiate raw memory from capabilities.
The "operating in hardware" is microcode in the 432 but RISC-friendly in the 960, but it is still there.
I am talking about the original 960MX here. Most of these features were dropped on the following 960 models, if I understood correctly. Those do not indeed have much in common with the 432.