It's really exciting what's going on with things like Tiny Tapeout/Efabless/ChipIgnite and whatever Google is sponsoring - I have a hard time keeping the players straight - as far as education and ambitious hobbyist use. You never know what will come from small designs, either.
That said, despite what some ASIC houses will tell you, I haven't seen the costs narrowing on commercial ASIC design to the point that realizing an SoC would be a substantial cost savings on an aggressively cost-optimized microcontroller-based design or IoT design. Being able to do a commercially viable small-to-medium-sized ASIC for a design that ships, say, less than 2M/year, would change a lot of things. It would be very interesting if that were the case in 5-10 years - what do you see from the IC design perspective?
For me, it was exciting, but now it's disappointing. The SkyWorks 130nm that TinyTapeout uses is ancient; they didn't really give away anything of value. The repository for that and the 90nm PDK haven't been touched in over a year. As I said, it's not substantial enough for me to think it's anything more than a PR stunt.
Agreed. Custom design is still prohibitively expensive, and most often not needed. That being said, older process nodes are getting cheaper to the point where the manufacturing cost is feasible. The problem remains EDA tooling, which may very well be the majority of the cost. Without more competition in that space, I don't see Cadence/Synopsys/Siemens bringing their prices down any time soon.
I think the point is to incentivize development of (open) software and educational content for chip design and verification, while keeping costs low. Once people have the skills to do this, and there is enough demand, then it would make sense to allow manufacture of chips with better feature sizes.
Besides 130 nm is plenty good for a lot of industrial applications.
> That being said, older process nodes are getting cheaper to the point where the manufacturing cost is feasible.
The older nodes have been cheap enough for quite a while now. Folks like Xfab have nodes where you can generate chips for about the same price as you can an injection mold.
Hadn't heard of Xfab. Very cool! By older nodes I meant like 28nm or 40nm. Looks like their smallest is currently 0.18 and that nodes been around since before I was even in school! It's definitely still useful for some applications, but not very competitive in my areas.
180nm and bigger is just fine for a lot of things--especially analog or MEMS.
Lots of guitar pedals would be interesting and they can use old school 1um+ technologies that tolerate +-9V. Low power stuff actually likes larger transistors as they have much smaller leakage.
There's lots of interesting stuff to do if you can sink the NRE. The problem is that the super expensive CAD tools don't let you amortize something that isn't a million+ units.
130nm is 1800€/mm^2 from global foundries. You need to order at least 10mm^2 meaning it costs 18000€ for 100 chips. 28nm will cost you at least 10000€ per mm^2. You get more transistors per dollar but the quantity of chips is the same.
That said, despite what some ASIC houses will tell you, I haven't seen the costs narrowing on commercial ASIC design to the point that realizing an SoC would be a substantial cost savings on an aggressively cost-optimized microcontroller-based design or IoT design. Being able to do a commercially viable small-to-medium-sized ASIC for a design that ships, say, less than 2M/year, would change a lot of things. It would be very interesting if that were the case in 5-10 years - what do you see from the IC design perspective?